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Logic Synthesis and Verification Algorithms

Gary D. Hachtel, Fabio Somenzi




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 | #1436963 in Books |  Springer |  1996-06-30 | Original language:English | PDF # 1 |  10.00 x7.00 x1.00l,3.10 | File type: PDF | 564 pages

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||1 of 1 people found the following review helpful.| A well-written exposition and text book|By Sally100|This is a very readable book that includes many helpful examples and exercises.
Hachtel's exposition is rigorous and Logic Synthesis and Verification Algorithmscrystal clear.|3 of 4 people found the following review helpful.| Good content, poorly written|By Y. Zhang|The b|From the Back Cover||In the last decade logic synthesis has gained widepsread acceptance by designers.  Formal verification is now advancing along the same path.  Computer aided design tools for logic synthesis and verification have become the primary

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates mo...

You can specify the type of files you want, for your gadget.Logic Synthesis and Verification Algorithms   |  Gary D. Hachtel, Fabio Somenzi. Just read it with an open mind because none of us really know.

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